Prof.  DI Aynul  Islam
University of Glasgow,  UK

Title: 3D FE MC Simulations of Nanosheet GAA pFETs: Effect of Strain, Quantum Corrections, and Interface Roughness

Abstract:

A classical concept of complementary metal-oxide-semiconductor (CMOS) transistors is approaching a scaling limit (proposed by Moore’s law) meaning that we are nearing the “end of the Roadmap of Semiconductors” [https://www.intel.com/content/www/us/en/silicon-innovations/moores-law-technology]. To continue the CMOS scaling, a further development of non-planar nanotransistors is of a pivotal importance. Multi-gate field-effect transistors (FETs) or wrapped-gate transistors are leading the CMOS scaling expanding the nanoscale technology into a real 3D space. As modern electronic devices are being miniaturised, FinFET technology has shown to be the leading architecture that maintains the high performance and efficiency due to exhibiting qualities such as a reduced leakage, a reduced short channel effect and lower power consumption than a planar transistor [A. Islam, B. Benbakhti, and K. Kalna, Monte Carlo study of ultimate channel scaling in Si and In_0.3Ga_0.7As bulk MOSFETs, IEEE Trans. Nanotechnol. 10, (2011) 1424-1432]

The channel mobility of p-type multi-gate field-effect transistors (FETs), including nanosheet and nanowire FETs aimed for sub-5 nm CMOS (complementary metal oxide semiconductor) technology nodes, is struggling to keep up with the channel mobility of n-type multi-gate transistor counterparts in a CMOS leading to serious designing challenges. This critical decline of hole mobility in the channel remains serious despite a sophisticated use of strain channel engineering. Therefore, the hole channel mobility increase is vital to continue the CMOS scaling.

Multi-gate FETs with the gate wrapped around, so-called gate-all-around (GAA) transistors, are being proposed and investigated as the only solution for sub-5 nm CMOS technology nodes [CMOS Nanoelectronics: Innovative Devices, Architectures, and Applications, ed. N. Collaert, Pan Stanford Publ., Singapore (2012)]. As modern electronic devices are being miniaturised, FinFET technology has shown to be the leading architecture that maintains high performance and efficiency due to exhibiting qualities such as a reduced leakage, a reduced short channel effects, and lower power consumption than a planar transistor. However, the FinFET architecture is unable to keep control of electrostatics when scaled further to the sub-5 nm CMOS technology nodes exhibiting increase in a leakage current and increase short channel effects.

The 3D MC/DD simulation toolbox, incorporating 2D Schrödinger equation quantum corrections (SEQC), will provide I-V characteristics which will be compared against experimental data by IBM [N. Loubet et al., Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET, VLSI Symp. Dig. Tech. Pap. 230-231 (2017)]. We will study the optimal channel materials enhanced by a strain engineering that can be used within a high-κ/metal gate stack in the nanosheet FETs. We will investigate what is the role of the roughness at the channel/high-κ/metal gate stack interface, how the optimal ratio in a binary SiGe and how uniaxial and biaxial strain in the channel will affect the hole transport in the channel of transistors.

Biography:

Aynul Islam awarded his PhD degree in electronics and electrical engineering from the University of Glasgow/Swansea University, United Kingdom. He has done research and development on the area of Monte Carlo Device Modelling of Electron Transport in nanoscale transistors. He finished his Master degree (Diplom Ingenieur, DI) in Technical Physics from the Johannes Kepler University, Austria. He has done his research on Erbium in Silicon Influence of Hydrogenation and Waveguiding. He has been continuing his research with analytical and numerical simulation using finite element, code developing, random matrix theory, quantum-mechanical treatments based on Schrödinger equation. His research interests on the area of Nanotechnology, Modelling and Simulation (Monte Carlo), Nanomaterials, Solar Cell, Photovoltaic, Photoluminescence Measurements, Heterostructure Devices using Lithography, Photonic Crystal. At present, he has been working as an Associate Professor in University of Electronic Science and Technology of China (UESTC), China, Glasgow College, Collaborated with University of Glasgow, United Kingdom. During his teaching and research he achieved the status of Fellow in Higher Education Academy, Bangor University, UK. He awarded recently Teacher of the year 2020 Student Led Teaching Awards, Bangor University, and Teacher of the year 2024 at the Glasgow College, University of Glasgow, UK. He got strong publication in high quality journal with strong impact factor, and published two books on nanotechnology and quantum mechanics.